1. Technical Field
Various embodiments of the present disclosure generally relate to a memory device and a method of operating the memory device, and more particularly to a memory device including select transistors and a method of operating the memory device.
2. Related Art
A memory device includes a memory cell array which stores data, a peripheral circuit which performs a program operation, a read operation, and an erase operation on the memory cell array, and a control circuit which control operations of the peripheral circuit.
The memory cell array may include vertical memory cell strings. The memory cell array may be subdivided into a plurality of memory blocks. The vertical memory cell strings may be connected between common source lines and bit lines. Each memory cell string may include source select transistors, memory cells, and drain select transistors connected in series between a common source line and a bit line.
The gates of the source select transistors, the gates of the memory cells, and the gates of the drain select transistors included in different memory cell strings are connected to source select lines, word lines, and drain select lines, respectively.
As a result, memory blocks of the memory cell array having vertical memory cell strings may be arranged in a vertical direction from a substrate. The memory blocks may share bit lines, source select lines, word lines, and drain select lines with each other.